Information display system

ABSTRACT

A system for the display of information on a cathode-ray tube or the like wherein the information comprises a plurality of lines of text comprising a number of characters and wherein each text line is formed by a plurality of scans. The system comprises a main memory for storing sets of bits wherein each set of bits represents a different one of all the characters to be displayed and an auxiliary memory for storing the sets of bits comprising the particular text line being formed on the screen of the cathode-ray tube. The auxiliary memory is operable to sequentially present each set of bits stored therein at its output during each scan comprising the particular text line. Decoding means responsive to the set of bits of the output of the auxiliary memory is provided to modulate the electron beam to form areas of the character represented by the set of bits during a particular scan.

United States Patent [72] Inventor Robert Sugarman New York, N.Y. [2|]Appl, No. 830,032 [22] Filed June 3, I969 [45] Patented May 25, 197!173] Assignee Sugar-man Laboratories, Inc.

Great Neck, N.Y.

[54] INFORMATION DISPLAY SYSTEM 3! Claims, 9 Drawing Figs. [52] [1.5. CI340/1715 [5|] Int. 606i 3/14 [50] Field olSeareh 340/172 5, 324; 235/I57 [56] References Cited UNITED STATES PATENTS 3,205,344 9/1965 Tayloret al 340/324X 3,394,367 7/l968 Dye 340/324 I KEYBOARD MAI N RRANGEMENTI RECIRCULATIN" o o o o o o I MEMORY O O O O O I l PrimaryExaminer-Raulfe B. Zache Attorney- Paul Fields ABSTRACT: A system forthe display of information on a cathode-ray tube or the like wherein theinformation comprises a plurality of lines of text comprising a numberof characters and wherein each text line is formed by a plurality CLOCKCIRCUITS CURSOR CONTROL CIRCUITS ;l MEMORY VIDEO RECIRC.

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CHARACTERS INVENTOR.

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SHEET 5 OF 6 FIG] v FOR REMOTE TRANsM|ss|ON OF MATERIAL MAIN MEMORYUNITS MUA-MUH MMAI ENA MMHI J A18 A19 A20 A21 A22 A23 A24 A25 A26 SHIFTREGISTER GAT TRNs LCS LOCAL CLOCK F|G.8 PROGRAM CONTROL g EOI SR2A-SR2H/PMO1 PC1 PMO2 --PC2 PMO3 r p -pC3 To r M04 LOGIC cuRsOR Z ME R PMQSELEMENT cOuNTER T 8 PMC NETWORK I 53%. PRE1- LEM U PRO1- PMOe PREs PROSI E MORY,

/PMO7 RMOa l -PCN J FBC INFORMATION DISPLAY SYSTEM This inventionrelates generally to a display system and, more particularly, pertainsto visual display terminal equipment which may be associated with dataprocessing systems.

An information display system of the type under consideration receivescoded information, usually in digitally or binary encoded form, from aninformation source such as a computer, a keyboard, a recording or thelike, and presents the same in human readable form on a display devicewhich may comprise the screen of a cathode-ray tube. Such displaysystems are gaining widespread use because, for example, an operator canview a message and correct any errors before transmitting theinformation to a remote receiver. At present, there are a number of suchdisplay systems available; however, these systems usually have a numberof disadvantages associated with their use.

To be more specific, in display systems employing a cathode-ray tubeeach individual scan of the electron beam across the face of the tubeproduces a slice of each character in a text line. Hence, the signalsrepresenting the characters comprising a text line must be presented toa video decoder sequentially. Additionally, since each text linecomprises a number of such scans, the sequential character signals mustbe repeated cyclically until the electron beam has traced out a completetext line. Present techniques include the use of a recirculating delayline memory to effect the sequential and cyclical presentation of suchcharacter signals to the video decoder. However, delay line memory unitsof the type described are costly and complex. Of more import is the factthat they require the use of sophisticated external circuits for properoperation.

ln order to ameliorate the above situation, it has been proposed toreplace such delay line memory units with core or random accessmemories. However the use of such devices becomes prohibitivelyexpensive.

Accordingly, a primary object of the present invention is to provide animproved information display system.

A more specific object of this aspect of the invention resides in thenovel details of the elements which provide an information displaysystem of the type described wherein a plurality of shift registerscomprise the circulating memory unit. The shift registers provide areliable and inexpensive memory in which data may be stored.

A further object of this aspect of the invention is the provision of aninformation display system which includes a memory unit which is easilyfabricated and is specifically adapted for modern mass productiontechniques.

As noted above, in information display systems of the type underconsideration, the signals representing the characters in the memoryunit must be presented to the video decoder sequentially and cyclicallyfor a number of scans of the electron beam of the cathode-ray tube whichare required to produce a text line. Where only one text line is to beproduced, a single memory unit is used to recirculate the signalsrepresenting the characters for the requisite number of scans. However,a problem is presented when it is desired to simultaneously display morethan one text line. Proposals have been made to simply provide a memoryunit for each text line. Thus, if a text line comprises 32 characters of6-bits per character and it is intended that It) text lines bedisplayed, then the complete memory would include 10 individual memorysubunits each comprising six storage devices of 32 character lengths. Itis obvious that such a system is unwieldy and expensive.

Accordingly, an object of another aspect of the invention is to providea system of the type under consideration which includes a main memoryfor storing all the signals representing the characters to be displayedand an auxiliary memory for storing the signals representing thecharacters comprising the text line being scanned, thereby providing arelatively inexpensive, reliable and easily produced memory unit.

In order to control and/or synchronize the electron beam of thecathode-ray tube in the subject information display systems, it has beenproposed to include command signals in the memory unit. This procedure,of necessity, requires high capacity memory units to record bothcharacter and control signals and, in addition, requires complexcircuits to decode the control signals and convert them into signalscompatible for use with the cathode-ray tube control circuits.

Accordingly, an object of a further aspect of this invention is toprovide an information display system wherein the memory unit storessignals representing only the characters to be displayed therebysubstantially decreasing the need for high capacity memory units.

Another object of this aspect of the invention is to provide aninformation display system in which an electron beam synchronizingsignal is derived from the clock circuits which control the memory unitthereby eliminating the need for sophisticated and expensive circuitryto decode stored command signals.

Accordingly, an information display system constructed according to thepresent invention is adapted to display information by the cyclicscanning of a writing means. The system comprises storage means forstoring characters divided into sets of information bits wherein thestorage means includes a main storage means for storing all of the setsof bits representing all of the characters to be displayed and auxiliarystorage means for storing the sets of bits representing the charactersto be displayed during a scan of the writing means and for sequentiallypresenting each set of bits at an output. Modulating means is connectedto the output of the auxiliary storage means responsive to the set ofbits appearing at said output for modulating the writing means to formareas of a character represented by the set of bits during the scanningof the writing means.

Additionally, a feature of this invention is the provision ofmicroprogramming techniques to further increase the flexibility of thesystem.

Another feature of this invention is to provide an information displaysystem which includes a display device having a moving cursor and amemory unit accessible in synchronism with the pattern of movement ofthe cursor wherein the cursor indicates the location at whichinformation will change on the display device when applied to the memoryunit from an input source such as a keyboard or a computer and the like.

Other features and advantages of the present invention will become moreapparent from a consideration of the following detailed description whentaken in conjunction with the accompanying drawings, in which:

FIGS. IA and 1B are illustrations showing the manner in which thecharacter patterns are displayed on the display device forming a part ofthe present invention;

FIG. 2 is a general block diagram of an information display systemconstructed according to the present invention;

FIG. 3 is a detailed schematic block diagram of the clock circuits ofthe present invention;

FIG. 4 is a detailed schematic block diagram of the memory and videoportion of the present invention;

FIG. 5 is a detailed logic diagram of the gate arrangement shown in FIG.4;

FIG. 6 is a schematic block diagram of the cursor control circuits shownin FIG. 2;

FIG. 7 is a schematic block diagram of an arrangement for thetransmission of information to a remote station; and

FIG. 8 is a detailed block diagram of the program control shown in FIG.6.

INTRODUCTION In general, an information display system constructed inaccordance with the present invention includes a display device such asa conventional cathode-ray tube having an electron beam which is adaptedto move across the face or screen of the tube in the conventional mannerand to illuminate various portions of the tube face or screen inaccordance with an input modulating signal. Each horizontal movement ofthe electron beam across the tube face, which is referred to as a scanline or scan, will produce a slice of the characters to be generated ina text line. For example, referring to FIG. 1B, which illustrates anenlarged section of a cathode-ray tube CRT face, it is noted that theelectron beam must make 2i vertically displaced scans across the face ofthe tube CRT to produce a single line of text. The first seven lines ofthe scan are usually blank, portions of the next seven scan lines areilluminated in accordance with the character to be generated, and theremaining seven scan lines are also blank. The blank scan lines areprovided to space one text line from the succeeding or preceding textline. The characters comprising a text line are produced by causing theelectron beam to make a plurality of dots on the face of the tube. Eachcharacter in the text line is ID dots or units wide. The first threedots are blank. The next five dots are illuminated in accordance withthe character to be generated, and the next two dots are blank. Thethree blank dots and the two blank dots are utilized to space onecharacter from the preceding and succeeding characters so each is spacedfrom an adjacent character by five dots.

As shown in FIG. IA, the display system of the present invention isadapted to generate l lines of text across the screen of the tube CRT.Additionally, each line of text comprises 40 characters of the typeshown in FIG. 18. Moreover, the electron beam is adapted to sweep out260 scan lines across the face of the tube.

It is emphasized that the quantities noted above (i.e., the number ofscan lines per text line, the total number of text lines, etc.) are forillustrative purposes only and are not to be interpreted as being alimitation of the present invention. That is, the different quantitiesmay be varied so that, for example, each text line comprises 42 scanlines of characters per text line. Alternatively, the scan lines may begenerated in the vertical direction rather than in the horizontaldirection.

DESCRIPTION OF THE SYSTEM In the description of the system the followingconventions will be employed:

1. Each signal line has a reference character equal to the signaldesignation; i.e., the CKA signal line carries the CKA signal;

2. When a signal is being generated it is considered present andequivalent to logical l or On the other hand, when a signal is not beinggenerated, it is considered absent and equivalent to logical 0 or 3. Thesignals transmitted throughout the system fall into two classes:

a. pulses such as the CKB pulses of short duration, and b. signals suchas INH signal of long duration, generally generated by a bistabledevice;

4. Throughout the description terminology such as words or digits aretransferred is employed; it should be understood that binary codedcombinations of signals or sets of bits representing the words or digitsare actually transferred;

5. Words are usually transferred through the system with their bits inparallel. For example, a word is transferred from scan line counter SLCon the LFSI, LFSZ, and LFS3 signal lines. However, to simplify the blockdiagrams, these three signal lines are generalized into a single lineLFSl-LFS3 which implies a cable of at least three signal lines. From therange of numbers in the signal character it is immediately known whatthe minimum number of signal lines are in the cable;

6. Terminology such as "setting a flip-flop" means switching ortriggering it to its on or I state wherein it generates a signal such asINH; and unsetting or "resetting a flipflop" means switching it to itsoff or 0 state;

7. The terminology character" is used to indicate a letter, a numeral,or a symbol such as an ampersand and the like.

GENERAL SYSTEM DESCRIPTION FIG. 2 illustrates, in generalized form, aninformation display system constructed according to the presentinvention. Accordingly, the display system includes a memory having amain recirculating memory which stores, in sequential order, the wordsor sets of bits representing all of the characters which are to beproduced on the screen of the tube CRT during any one picture frame. Thewords are recirculated through the main memory so that any one word ispresented at the output of the main memory once during each cycle.Additionally, the memory includes an auxiliary recirculating memorywhich is adapted to store and recirculate the words representing thecharacters to be produced in any one text line. Similarly to the mainrecirculating memory, the words in the auxiliary recirculating memoryare cyclically available at the output thereof. The output of theauxiliary recirculating memory is connected to the video circuits whichoperate upon the words representing the characters which are presentedat the output of the auxiliary recirculating memory and converts thesewords into control signals for the cathode-ray tube CRT to reproduce thecharacter on the face of the screen. In practice, the main recirculatingmemory and the auxiliary recirculating memory comprise shift registerswhich are adapted to store the words representing the characters orcharacter words in individual cells and to move the words from cell tocell under the control of the clock circuits.

In the present embodiment, the auxiliary recirculating memoryrecirculates 40 words comprising a text line of characters for a totalof 2i cycles corresponding to the 21 scan lines per text line of thedisplay device or cathode-ray tube CRT. At the end of the 21 cycles, theclock circuits cause the next 40 words or sets of bits representing thefollowing text line of characters to be loaded from the mainrecirculating memory into the auxiliary recirculating memory. Thus,these newly entered words recirculate in the auxiliary recirculatingmemory for a total of 2! cycles and the procedure is again repeated toload into the auxiliary recirculating memory, from the mainrecirculating memory, the next succeeding 40 words representing thecharacters comprising the next succeeding line of text.

A moving cursor or trace is also produced on the face of the tube CRT toindicate the character location at which new information will appearwhen it is introduced into the memory. The cursor is controlled by thecursor control circuits. Thus, if it is desired to introduce a newcharacter from a source such as the keyboard arrangement or a magnetictape source (not shown) or the like, the cursor control circuits enablethe main recirculating memory to receive the new word at a point in thecycle of the main recirculating memory corresponding to the particularcharacter location on the face of the tube CRT which is flagged by thecursor.

Additionally, a program control (not shown in FIG. 2) is provided tocause various portions of the system to perform various functions.

DETAILED DESCRIPTION OF THE CLOCK CIRCUITS (FIG. 3)

The clock circuits shown in FIG. 2 are illustrated in detail in FIG. 3.Where a particular counter is to produce a pulse, such as the CSP pulse,when the counter has reached a predetermined count, it is to beunderstood that the appropriate outputs of the individual registers inthe counter are connected to an AND gate so that when the particularcount is reached, all inputs to the AND gate will be energized wherebythe AND gate produces the particular output pulse.

The clock circuits include a clock CK which may be a crystal controlledoscillator and, in the particular example under consideration, producesa 7 MHz./s signal. The clock CK produces an output signal CKA which isapplied to the input of a dot counter DC. The dot counter is aconventional counter and produces one output pulse CKB in response to 10input CKA pulses. The dot counter determines the width of a particularcharacter on the screen of the tube CRT which, as noted in thedescription of FIG. 1, is dots wide.

Additionally, the dot counter DC produces a cursor strobe pulse CSP whenthe counter reaches a count of five.

The output pulses CKB of the dot counter DC are applied to the input ofa character counter CC. For every 50 input CKB pulses the charactercounter CC produces one output pulse CKC. The character counter CCdetermines the number of characters appearing in a text line. The first40 CKB pulses applied to character counter CC represent the 40characters appearing in a text line. The remaining l0 pulses required toreach a count of S0 occupy a time interval which is equal to the timeinterval required for the retrace of the electron beam between scanlines in the tube CRT. Thus, a pulse CKC will be produced at thecompletion ofeach scan line or scan including the retrace time.l-lOwever, as used herein, the word scan includes retrace time unlessotherwise noted.

The character counter CC produces a pulse INS when the counter reaches acount of 40, representing completion of the sweep of the electron beamthrough the 40 characters comprising a text line. The pulse W8 isapplied to the set terminal S of a bistable device or flip-flop FF] toset the flip-flop. Accordingly, the flip-flop produces an [M1 signal atits 1 output terminal when it is moved to the set state. The flip-flopis reset by the CKC pulse so that the INH signal is present only duringthe last ten C KB pulses.

The output of the character counter CC is connected to one inputterminal of an AND gate Al. The output terminal of the gate Al isconnected to the input terminal of a scan line counter SLC. The scanline counter SLC produces one output pulse CKD in response to 2l inputpulses CKC. (For the present, it is assumed that the other inputterminal ofthe AND gate Al is energized or enabled so that that CKCpulses pass through the gate Al to the counter SLC.) The scan linecounter SLC essentially counts the number of scans of the electron beamin the tube CRT and produces a pulse CKD after a text line comprising 2|such scans has been completed. (For ease of reference, a scan line isassumed to include the retrace time, as noted above).

Additionally, the scan line counter SLC is adapted to produce a loadauxiliary memory pulse LAM when the first CKC pulse during a countingcycle is received by the counter. The scan line counter also producesline finder signals LFSl- LFS3. The signals LFS represent a 3-bit codeto designate which particular slice of the characters are being scannedthrough by the electron beam. To be more specific, the characters occupyscan lines 8-15 in the text line as shown in FIG. 1B. The signalsLFSl--LFS3 indicate which one of the scan lines 8-l5 the electron beamis tracing through at that particular moment.

The scan line counter SLC also produces a pulse CLP representing thecursor line position pulse. This pulse is produced when a count of 17has been reached so that the cursor is produced in the seventeenth scanline of the text line or, in other words, the cursor trace appears twoscan lines below the particular character with which it is associated.

The output of the scan line counter SLC is connected to the input of atext line counter TLC. The text line counter is a conventional counterand is adapted to produce one output pulse CKE in response to l2 inputCKD pulses. Although only [0 text lines are produced on the screen ofthe tube CRT the text line counter TLC counts [2 CKD pulses tocompensate for the blanking period during the retrace of the electronbeam. The reason for this operation will become apparent from aconsideration of the description of the memory circuits of the presentinvention hereinbelow.

As noted hereinabove, the infonnation display system of the presentinvention is adapted to be utilized in conjunction with a conventionalcathode-ray tube CRT. In practice, 260 scan lines are produced acrossthe face of the tube for each picture frame. However, it is to be notedthat the pulse CKE is produced after l2 times 21 or 252 scan lines havebeen counted.

To have the first line of characters properly displayed at theinitiation of each scan, it is necessary that the main memoryrecirculate an integral number of cycles for each complete scan of thecathode-ray tube CRT. In the example under consideration, the mainmemory completely recirculates or completes a cycle every l0 scan lines.Assuming that vertical blanking at the top and bottom of the scanoccupies an additional 5 times 10 text lines, then there are 10X2 1+5Xl0or 260 scan lines produced during one picture frame. Thus, tosynchronize the clock circuits with the electron beam and the memoryunit, an additional eight scan lines are counted after the CKE pulse isproduced so that the total scan line count is 252+8 or 260.

To be more specific, in order to synchronize the operation of the clockcircuits with the electron beam of the CRT, an auxiliary scan linecounter is utilized to count an additional eight scan lines after thepulse ,CKE has appeared. More particularly, the output terminal of textline counter TLC is connected to the set terminals ot'a flip-flop FFZ.The l output terminal of the flip-flop FFZ is connected to one inputterminal of an AND gate A2. The other input terminal of the AND gate A2is connected to the output terminal of the character counter CC so thatthe CKC pulses representing the completion of scan lines are applied tothe AND gate A2. Accordingly, when the CKE pulse is produced, theflip-flop FFZ is set to energize one terminal of the AND gate A2.Thereafter, as the pulses C KC appear at the other terminal of AND gateA2, they are applied to an auxiliary scan line counter ASLC which isconnected to the output of the gate A2. The counter ASLC is aconventional counter and produces an output pulse RES when eight pulseshave been counted. Additionally, the 1 output terminal of the flip-flopFFZ is connected to the input terminal of an inverting or paraphaseamplifier IV], the inverting output terminal of which is connected tothe other terminal of the AND gate Al. Thus, when the flip-flop FFZ isset, the AND gate AI will be disabled and no further pulses will passthrough to the scan line counter SLC.

When eight scan lines have been counted by the counter ASLC, the outputpulse RES produced by this counter will be applied to the reset terminalR of the flip-flop FF2 to reset the flip-flop so that the 1 outputsignal is removed. Accordingly, the terminal of AND GATE A] which isconnected to the inverting amplifier lVl will again be energized so thatpulses CKC will pass through to scan line counter SLC.

A synchronizing pulse SYNC is applied to the vertical deflectiongenerator and the sweep signal generator to synchronize the movement ofthe CRT electron beam with the operation of the clock circuits in theconventional manner. The SYNC pulse is derived from the charactercounter CC and the auxiliary scan line counter ASLC. More specifically,a pulse SGI, which may be produced during the last 10 counts of thecharacter count CC (i.e., during the electron beam retrace period) isapplied to the S terminal of a flip-flop FF3 to produce the SGS signalat the 1 output thereof. Additionally, the character counter CC producesan SGF pulse after the 86] pulse but before the next occurring CKC pulsewhich is ap plied to the R terminal of flip-flop FF3 to reset flip-flopFF3.

Similarly to the character counter CC, the auxiliary scan line counterASLC produces a VDI pulse during the eight scan line count which isapplied to the S terminal of a flip-flop FF4 whereby a VDS signal isproduced at the 1 output. The auxiliary scan line counter ASLC alsoproduces a VDF pulse after the VDI pulse but before the RES pulse whichis applied to the R terminal of FF4 to reset flip-flop FF4.

As shown in FIG. 4, the VDS and the SGS signals are applied torespective terminals of an OR gate 03, the output of which is thesynchronizing pulse SYNC, thereby to synchronize the operation of thetube CRT with the other elements of the system.

DETAILED DESCRIPTION OF THE MEMORY (FIG. 4)

In the present embodiment, each character is represented by an 8-bitword or set of eight information bits. The first 6 bits are utilized todesignate the particular character which is to be produced on the faceof the tube CRT. The seventh bit may be used for parity purposes and theeighth bit in the word may be used as a command signal, for example, toproduce a reverse field effect on the screen of the cathode-ray tube orto denote that the character is not to be erased. Accordingly, there isprovided eight identical memory units MUA-MUH which produce the signalsAMAAMH at their respective outputs. Each one of the signals AMAAMHrepresents a bit in the 8-bit word noted above so that the signalsAMAAMH taken in parallel form one word. Since each of the memory unitsMUA-MUH is identical, only the memory unit MUA is shown and described indetail.

The memory unit MUA comprises a Main Memory Section and an AuxiliaryMemory Section. The Main Memory Section includes Main Memory A which, inpractice, comprises a shift register having provision to store 400 bitsof information, each bit comprising one bit of the word representing thecharacters which are to be produced across the face of the tube CRTduring any one picture frame. That is, as noted above, each line of textdisplayed comprises 40 characters and, since there are 10 lines of textwhich are displayed during a picture frame, the tube CRT can display 400characters at any one time. Hence, Main Memory A stores 1 bit of thewords representing all of the characters which may be displayed at anyone time. It is to be noted that if the capacity of the tube CRT ischanged, then the capacity of the Main Memory A will likewise be changedso that the Main Memory A stores as many word bits as the number ofcharacters which may be displayed during a picture frame.

The output terminals of the Main Memory A is connected to the input ofgate G1 via an MMAO signal lead. The output of gate 01 is connected tothe input terminals of Main Memory A via an MMAI signal lead. The shiftterminal of Main Memory A is connected to the output of an AND gate A4which produces a shift pulse CAO when the input terminals of the gateare enabled. One input terminal of the AND gate A4 is connected toreceive the pulse CKB. The other terminal of AND gate A4 receives aninverted lNl-l signal via an inverting or paraphase amplifier 1V2. Thus,when the lNH signal is absent and a CKB pulse is received, a shift pulseCAO will be gated to the shift terminal of Main Memory A thereby causingthe shift registers in Main Memory A to shift the information therein onposition. Under normal conditions, the lead MMAO is connected to thelead MMAI through the gate G1. Thus, the output signal MMAO is applieddirectly to the input of the Main Memory A via the lead MMAI to providea recirculating memory.

That is, when the signal leads MMAO and MMA] are connected togetherthrough the gate G1, the signal appearing at the output of Main Memory Ais applied directly to the input of the Main Memory. When the next shiftpulse CAO occurs, the next signal appearing at the output of Main MemoryA is similarly applied to the input thereof so that the signalsrecirculate through the main memory. Moreover, since the AND gate A4produces a shift pulse only during the time that characters arepresented on the face of the CRT and not during retrace, it will beobvious that each word bit representing a character will be produced atthe output (input) of the Main Memory in synchronism with theinformation producing movement of the electron beam.

The Auxiliary Memory Section includes an Auxiliary Memory A whichcomprises a 50-bit shift register. The Auxiliary Memory A is adapted tostore the 40 word bits associated with the characters in a line of textand, in addition, contains l0 blank cells. The output of the AuxiliaryMemory A is connected to the input terminal of a gate 62 via the signallead AMAO. The output of gate 02 is connected to the input terminals ofAuxiliary Memory A via the lead AMA.

Under normal operating conditions, the signal AMAO is connected throughto the signal lead AMA via the gate G2. Accordingly, the output signalappearing at the output terminals of Auxiliary Memory A will be appliedto the input thereof in a manner similar to the operation of Main MemoryA. The shift pulse CKB is applied to the shift terminal of AuxiliaryMemory A so that for each shift pulse received, the word bit appearingat the output will be applied to the input of Auxiliary Memory A therebyto provide a recirculating auxiliary memory. Additionally, this sameoutput-input signal will appear at the output of memory unit MUA via theAMA lead.

It is to be noted that the Auxiliary Memory A is shifted by the CKBpulses and that 50 CKB pulses are required to produce a CKC pulserepresenting the completion of a scan line. Thus, the reason forproviding l0 blank positions in the auxiliary memory will not becomeapparent. That is, during the first 40 CKB pulses the word bitsassociated with the characters appear on the lead AMA. However, duringthe last 10 CKB pulses, which occur during retrace of the electron beam,the 10 blank positions appear on the output lead AMA. Thus, when thenext scan line begins, the Auxiliary Memory A will produce the word bitassociated with the first character to be reproduced on the screen ofthe tube CRT so that the Auxiliary Memory is maintained in synchronismwith the electron beam.

Additionally, it is to be noted that the Main Memory A does not includeany blank positions but the Main Memory is not shifted during theoccurrence of the last [0 CKC pulses. Thus, the Main Memory will bemaintained in synchronism with the auxiliary memory. Furthermore, sincethe respective shift pulses CAO and C KB are applied to the respectivemain and auxiliary memory portions of each of the memory units MUA- -MUHsimultaneously, it will be obvious that each memory unit will be steppedor shifted in synchronism with each other memory unit so that all eightbits representing a character will be presented in parallel to acharacter generator CG via the signal leads AMAAMH.

Summarizing the above, the auxiliary memory stores 40 characters and themain memory stores 400 characters. To put this another way, theauxiliary memory may be thought of as storing M (N) characters wherebythe main memory therefore may be thought of as storing M (N+X)characters where M is greater than one and N and X are greater thanzero.

A feature of the present invention is to fabricate the main andauxiliary memories of each of the memory units MUA- MUH from shiftregisters thereby to provide a device which is ideally adapted for largescale integration techniques. Hence, the memory units may bemanufactured relatively easily and cheaply. Additionally, these memoryunits are flexible in operation.

As noted in the description of the clock circuits, the LAM pulse isproduced at the initiation of the first scan line by the scan linecounter SLC and has a duration which is equal to the time that isrequired for the electron beam to trace through the first scan line of atext line plus the retrace time. During the time interval that the LAMpulse is present and applied to gate G2, the connection between the AMAOlead and the AMA lead is broken and a connection is made between theMMAI and the AMA lead. Thus, as the shift pulses CAO and CKB occur, theword bit entering the Main Memory A will also enter Auxiliary Memory Aand will appear on the output lead AMA.

To be more specific, FIG. 5 illustrates an embodiment which the gate G2may take. Accordingly, there is provided an inverting or paraphaseamplifier [V3 which receives the pulse LAM at the input terminalsthereof. The inverting output terminal of the amplifier [V3 is appliedto one input terminal of AND gate A4. The other terminal of AND gate A4receives the AMAO signals from the output of Auxiliary Memory A. Theoutput terminal of gate A4 is connected to one input terminal of OR gate01, the output terminal of which is connected to the input terminal ofAuxiliary Memory A via the signal lead AMA. The noninverting outputterminal of amplifier IVS is connected to one input terminal of an ANDgate A5. The other input terminal of the gate A is connected to the MainMemory A signal lead MMAI. The output terminal of the AND gate A5 isconnected to another input terminal of OR gate (H.

In operation, when the LAM pulse is absent, signals will be passed tothe input terminal of the Auxiliary Memory A from the lead AMAO, gatesA4 and 01 to produce the recirculating auxiliary memory noted above.However, when the LAM signal is present, thereby signifying that theAuxiliary Memory A is to be loaded from the Main Memory A, the MMAIsignals will be passed through the AND gate A5 and OR gate 0| to theinput terminal of the Auxiliary Memory A thereby to load the same.Simultaneously therewith, the same signal will appear at the output ofmemory unit MUA via the AMA lead.

The LAM pulse occurs once during every 21 scans of the electron beam.During the presence of the LAM pulse 40 CAO shift pulses will occur sothat the 40 bits associated with the characters to be produced in thetext line will be loaded into Auxiliary Memory A. Moreover, these databits will recirculate through Auxiliary Memory A for 21 cycles. Hence,the data bits associated with the characters comprising a text line willbe available on the AMA signal lead sequentially and cyclically for atotal of 2 I cycles.

After the electron beam has traced through the 21 scan lines comprisinga text line, the LAM pulse again will be present so that the AuxiliaryMemory A may again be loaded from the Main Memory A.

Since the Auxiliary Memory A stores 40 bits of information or data andthe LAM pulse is present during only 40 CAO shift pulses, the full textline of word bits will be introduced into the Auxiliary Memory A. Anyone particular bit in Auxiliary Memory A will be shifted a total of 50times during any one scan line while a bit in the Main Memory A will beshifted a total of 40 times. Since the memories go through 2| cycles, abit in Main Memory A will be shifted a total of 2IX40 or 840 timesduring the generation of a text line on the face of the tube CRT. Sincethe Main Memory A stores only 400 bits of data, it will be obvious thatwhen the LAM pulse again appears atter the twenty-one scan lines, theinformation which is now loaded into the Auxiliary Memory A willcorrespond to the next line of text to be displayed.

Accordingly, another feature of the invention is the provision of anauxiliary memory section which recirculates the information required forthe generation of a text line during the scanning of the text linethereby to eliminate the need for repetitive main memory sections foreach line of text and to produce an extremely fine display withoutsubstantially increasing the storage capacity of the memory units.

VIDEO CIRCUITS (FIG. 4)

The video circuits include the character generator CG. The charactergenerator CG may be a read-only memory which coordinates the parallelinput signals AMAAMH at its input terminals with the LFSI-LFSI! signalsindicating the particular line being scanned and produces paralleloutput signals on the signal leads CGA-CGE, respectively, representing,in binary forrn, the portions of the scan line which are to beilluminated by the electron beam. To be more specific, the signalsAMAAMH indicate the particular character to be reproduced on the face ofthe tube CRT. The LFSI-LESS signals indicate the particular line beingscanned. These signals cause the memory to read out on the leads CGA CGEsignals representing the slice of the character to be produced on thescreen of CRT in binary form. Moreover, these CGA- -CGE signals willchange 40 times during each scan line in accordance with the signalsAMAAMh associated with the memory units MUA-MUH so that all 40characters will be produced on the screen of the tube CRT during thegeneration of a text line. It is to be noted, however, that thecharacter generator CG will not produce output signals during the firstseven and last seven scan lines as noted above in the discussion of FIG.IB since the signals on leads LFSI LFS3 will be interpreted to indicatethat no signals are to be produced during these scans.

The leads CGA-CGE are individually connected to an input terminal of therespective AND gates A6-Al0. The other input terminal of the AND gatesA6-Al0 are adapted to receive the CKB pulses. The output terminals ofthe AND gates A6-A 10 are connected to particular registers in a I0- bitshift register SRI having a parallel preset input and a serial output.

More specifically, the output terminals of the respective AND gatesA6-Al0 are connected to the registers of the shift register SRl so thatthe signals appearing at the output terminals of A6-AIO will be appliedto the fourth through eighth cells in the shift register. The firstthree cells and the last two cells of the shift register SR1 are alwaysleft blank. Pulses CKA are applied to the shift terminal of the shiftregister SR1 to serially shift the information in the register to theoutput lead SRO. The output lead SRO is connected to one terminal of anAND gate All. The other terminal of the gate All is connected to theinverting terminal of an inverting amplifier N4, the input terminal ofwhich is adapted to receive the INH signal. Thus, if the lNH signal isabsent, the SRO signal will be gated to the cathode or grid of thecathode-ray tube CRT through an OR gate 02. When the INH signal ispresent, as during the blanking or retrace period, the AND gate All isdisabled thereby preventing the passage of any SRO signals.

Each CKA signal represents a dot or unit of a character, a characterbeing ten dots wide. Thus, since the first three cells in shift registerSR] are empty, the first three SRO signals during the generation of acharacter will be blank. The next five SRO signals will represent theslice of the character being generated and will modulate the electronbeam to produce an area of the character. Thus, if a-I signal appears onthe lead SRO, the electron beam will produce a dot. However, if a 0signal appears on the lead SRO during these next five CKA shift pulses,the electron beam will not illuminate the screen of the CRT. Theremaining two blank cells will be shifted out by the last two CKA pulsesto produce the space of two dots on the screen, as noted above inconjunction with the description of FIG. 1B.

DETAILED DESCRIPTION OF KEYBOARD ARRANGEMENT The keyboard arrangementincludes a standard keyboard KBD which is adapted to produce signalsrepresenting the particular characters to be entered into the memoryunits MUR- -MUH or command signals for the program control. In practice,the keyboard KBD is adapted to represent the character in binary formutilizing the standard ASCII code (the latter referring to the AmericanStandard Code for Interchange of Information recommended by the IEEE).The ASCII code represents a character by a 7-bit word. However, as notedabove, in the present system the video portion of the character isrepresented by a 6-bit code with the two other bits of the wordrepresenting other information. Thus, the first bit is removed in theword representing the character struck on the keyboard KBD and two otherbits of information are added by the keyboard. The output of thekeyboard is applied to a parallel or serial-input parallel-output 8-bitshift register SR2. That is, information may be introduced into theshift register SR2 in either parallel form or serial form depending uponthe source of information.

For example, when information is entered into the shift register SR2from the keyboard KBD, the information is entered in parallel. However,the serial input of the shift register SR2 may be connected to a remoteline so that information may be transmitted in serial form from a remotecomputer, magnetic tape, or the like, to the information display systemof the present invention. Thus, the RE! pulses which are applied to theserial input of shift register SR2 represent such serial information. Ashift pulse REH, which may be produced from a local clock or the like isused to shift the information pulses RBI in shift register SR2.

The output terminals of the shift register SR2 are individuallyconnected to respective gates (ll of each of the memory units MUA-MUHvia the respective leads SR2A- SR2H.

The gate G1 is similar in construction to the gate G2 shown in detail inFIG. 5. However, the input lead of the gate G1 is connected to theoutput of an AND gate A18, an input terminal of which receives a GATpulse from the cursor control circuits shown in FIG. 6. The other inputterminal of the gate A18 is connected to the inverting terminal of aninverting amplifier IVS, the input terminal of which receives an STPsignal from the program control.

During normal operation, in the absence of the GAT pulse and the STPsignal, the signals appearing at the output of Main Memory A arecirculated back to the input of the Main Memory A. However, when the GATpulse is present and the STP signal is absent, the gate 01 passes thesignal on lead SRZA to the input of Main Memory A so that theinformation in Main Memory A is updated.

The STP signal is generated by the program control, in the manner notedbelow, so that when the STP signal is present, the AND gate A18 isdisabled. Hence, no character recorded in the memory can be erased orchanged even though the GAT pulse is applied to the gate All.Alternatively, the STP signal may be generated by setting a flip-flop bymanually operating a switch on the keyboard KBD to protect the words orsets of bits in the memory.

DETAILED DESCRIPTION OF THE CURSOR CONTROL CIRCUITS (HO. 6)

The cursor control circuits are illustrated in FIG. 6 and function toproduce a trace or cursor on the face of the screen of the CRT at thepoint that new information will appear on the screen. The particularform of the cursor is a line which is spaced below the characteroccupying the position at which the new information will appear or issimply an underline if no character occupies that particular position.

The cursor control circuits include a 400-bit binary counter CBC whichcounts the CA pulses applied to its count input. Additionally, thecounters may be preset to a specific count or may be incremented ordecremented in accordance with signals appearing on the leads PCOl andPCOZ. Since the counter CBC is driven by the CA0 pulses, it will beobvious that the cursor counter will be stepped in synchronism with theMain Memory A and, therefore, the Auxiliary Memory A.

More particularly, the 400-bit counter CBC comprises a 40- bit binarycounter FBC and a 10-bit binary counter TBC. The counters FBC and TBCare connected to the respective input terminals of an AND gate Al 1.Accordingly, when the counter CBC reaches a particular count both inputsof the AND gate All will be energized so that the gate will pass a GATpulse. This GAT pulse will be produced once every 10 scan lines sincethe counter will have gone through a full cycle of operation during the10 scan lines (i.e., 40 CAO pulses per scan line [representing the 40characters per scan line] X 10 scan lines equals 400 CAO pulses).Additionally, when a particular count is reached by the 40-bit counterFBC, the counter FBC produces a CHP pulse. Moreover, the CHP pulse willbe produced once during each cycle of the counter FBC so that the cursorcounter CBC produces 10 CHP pulses for every GAT pulse produced sincethe 40-bit counter FBC goes through 10 cycles of operation during a400-bit count of the counter CBC.

The GAT pulse is carried by the GAT signal lead which is connected toone input terminal of an AND gate A12, the other input terminal of whichreceives the LAM pulse. Since the LAM pulse is available only during thefirst scan line in a text line and the GAT pulse is produced once everyl0 scan lines, the GAT and LAM pulses will coincide only during thegeneration of the text line which includes the position to be identifiedby the cursor. The foregoing may best be understood by an example.

Thus, assuming that the cursor is to be displayed in the third textline, the LAM pulse will be available during scan lines I, 22, 43, 54,etc. lfit is assumed that the GAT pulse is produced during the thirdscan line on the face of the tube CRT, it will occur during scan lines3, 13,23, 33, 43, 53, etc. Thus, coincidence of the pulses GAT and LAMwill occur during the generation of the first scan or scan line of thethird text line and the gate A12 will pass a SAM pulse to the S terminalofa flip-flop FPS. The flip-flop FFS is reset by the next occurring CKEpulse which is applied to its reset terminal R.

The particular position of the cursor once the text line has beenselected by the GAT and LAM pulses is determined by the CHP and CLPpulses. Thus, when flip-flop FFS has been set, a signal will appear atthe 1 output to enable one input terminal of an AND gate A13 connectedthereto. The gate A13 will pass a pulse CHC upon the occurrence of theCHP pulse which is applied to its other input terminal. As noted above,the CHP pulse is produced once every 40 CAO pulses and corresponds tothe character position to be underlined by the cursor trace.

The CHC pulse is applied to one input of an AND gate A14, the otherinput of which receives the CLP pulse which is available during thegeneration of the seventeenth scan line. Thus, when the AND gate A14 isenabled by the CHC and CLP pulses, it passes the CVP pulse which isapplied to the tube CRT through the OR gate 02 to modulate the electronbeam whereby the cursor trace is produced on the screen.

As noted above, the GAT pulse is applied to the gate 01 (FIG. 4) of thememory so that the memory will be updated upon the occurrence of the GATpulse. Since the Main Memory A is shifted by the CA0 pulses which arecounted by the cursor counter CBC, it will be obvious that the cursorwill appear at the point at which new information will be entered intothe memory.

The movement of the cursor on the face of the tube CRT is controlled bya program control PC which controls the state of the elements comprisingthe counter CBC. Thus, it it is desired to move the cursor one characterposition to the right on the screen after information has been enteredinto the memory, the counter CBC is decremented one count after the GATpulse has been produced. For example, if the first GAT pulse is producedafter l0 CAO pulses have been counted and the counter is decremented onecount, the next GAT pulse will be produced after 400 plus I l CAO pulseshave been counted. This has the effect of moving the cursor one positionto the right on the screen. if it is desired to move the cursor to theleft, the counter CBC is incremented one bit by the program control PC.

More specifically, the GAT pulse is applied to the S terminal of aflip-flp FF6 to set the same. The flip-flop is reset by the next CAOpulse applied to its R terminal. The 1 output of FF6 is connected to oneinput terminal of an AND gate A15, the other input terminal of whichreceives the cursor strobe pulse CSP. When the gate A15 is enabled itpasses an enabling pulse GATD to respective inputs of AND gates A16 andA17. The other input terminals of the respective AND gates A16 and A17are connected to the program control PC via the respective leads PC] andPCZ. The output of the gates A16 and 17 are connected to the respectivecounters FBC and TBC via leads PCOl and PC02, respectively, so thatthese counters may be updated when the gates A16, A17 are enabled.

Thus, if the cursor is to move to the right one position when newinformation is introduced into the memory, the program control willproduce signals which will cause the counter CBC to decrement 1 bit whenthe control PC is connected through to the counter CBC upon occurrenceof the enabling pulse GATD.

Alternatively, the leads PCO1 and PCOZ may comprise cables of leads sothat signals appearing on the leads will preset a will be seriallyapplied to the output terminal via the lead TRNS which, in turn, may beconnected to the local telephone lines via a data phone or the like sothat the information may be transmitted to a remote point.

APPENDIX AND gates used throughout the system are of the coincidencetype, which may, for example, comprise a crystal diode network whichfunctions to receive input signals via a plurality of input terminalsand to pass an output signal when, and only when, input signals arepresent at each one of its input terminals.

The OR gate for circuits used throughout the system may be crystal diodenetworks which function to pass a signal received at any one of itsinput terminals to its output ter minal. Although it is not always shownthat the output of the AND gates and the OR circuits are fed throughamplifiers, it is possible that noninverting conventional direcbcurrentamplifiers may be connected to the output of these units when ever poweramplification is required. In some cases, when both the signal and itsinverse are simultaneously required, it is then desirable to employconventional paraphase direct-current amplifiers to perform the requiredoperation. In some instances, throughout the system, only the inverse ofsignals are required. Accordingly, the amplifiers would be conventionalsignal inverters for inverting direct-current signals.

The flip-flops employed throughout the system are conventionalflip-flops having a set input S, a reset input R, a one's output 1 and azeros output 0. When the flip-flop receives a signal at the set input 5,it transmits a signal from its one's output l. When the flip-flopreceives a signal at its reset input R it is cleared and transmits asignal from its zero 5 output 0.

The counters employed throughout the system are conventional binarycounters having a count input, a clear input R, a ones output 1 and azeros output 0. Each time the counter receives a signal at its countinput, it changes states. For example, if the counter is initiallycleared by a signal at its clear input R, its zeros output 0 transmits asignal and its ones output 1 transmits no signal. When the first signalis received at its count input, the counter changes states wherein asignal is transmitted from its one 's output 1 and no signal istransmitted from its zeros output 0. When the counter then receivesanother signal at its count input, it again changes stable stateswherein the zeros output 0 transmits a signal and the one's output 1also transmits a signal. For the sake of clarity throughout thedisclosure, it should be noted that all of the counters and all of theflip-flops have an input (not shown) which is connected to an initialclear line so that at the start of operation all of the flip-flops andthe counters are switched to their clear states; that is, all of theirzeros outputs 0 are transmitting signals.

Further, since the various elements shown in system are made up ofstandard components, and standard assemblies, reference may be had to"High Speed Computing Devices," by the Staff of Engineering ResearchAssociates, Inc. (Mc- Graw-Hill Book Co., Inc. 1950); and appropriatechapters in Computer Handbook" (McGraw-Hill, I962) edited by Harvey D.Huskey and Granino A. Corn, and for detailed circuitry, to the examplesin Principles of Transistor Circuits," edited by Richard F. Shea,published by John Wiley and Sons, Inc. New York and Chapman and Hall,Ltd., London, 1953 and 1957. In addition, other references are: forsystem organization and components: "Logic Design of Digital Computers,"by M. Phister, Jr., (John Wiley and Sons, New York); ArithmeticOperations in Digital Computers," by R. K. Richards (D. Van NostrandCo., Inc., New York). For circuits and details: Digital ComputerComponents and Circuits," by R. K. Richards (D. Van Nostrand Co., lnc.,New York).

While a preferred embodiment of the present invention has been shown anddescribed herein it will become obvious that numerous omissions, changesand additions may be made in such embodiment without departing from thespirit and scope of the present invention.

lclaim:

l. A display system for displaying at least two lines of characters on amedium which requires a plurality of scans of a writing means to produceeach one ofsaid lines of characters comprising, in combination, storingmeans for storing said characters as respective sets ofinformation bits,and decoding means for converting the information bits in any one ofsaid sets into signals for modulating said writing means to produce thecharacter represented by said one set of information bits during saidplurality of scans, said storing means comprising a first storage devicehaving output terminals for storing the sets of bits representing thecharacters to be displayed and for producing said sets of bits atrecurrent intervals at said output terminals, and a second storagedevice connected to said output terminals of said first storage devicefor storing the sets of bits representing the characters to be displayedin one of said lines and for sequentially applying the stored sets ofbits in said second storage device to said decoding means during eachone of said plurality of scans.

2. A display system as in claim I, in which said second storage deviceincludes input terminals and output terminals and is operable torecirculate the sets of bits stored therein and sequentially presenteach one of said sets of bits at said output terminals in response to ashift pulse, and shift pulse generating means for applying shift pulsesto said second storage device.

3. A display system as in claim 2, in which said first storage deviceincludes input terminals and is operable to recirculate the sets of bitsstored therein and sequentially present each one of said sets of bits atsaid output terminals in response to a shift pulse, and connecting meansfor connecting said shift pulse generating means to said first storagedevice to apply said shift pulses to said first storage device.

4. A display systems in claim 3, in which said second storage deviceincludes second storage gate means for normally connecting said secondstorage device output terminals with said input terminals and forconnecting said second storage device input with said first storagedevice output terminals in response to a second storage load signal, andsecond storage load signal generating means responsive to the completionof said plurality of scans of the writing means for applying said secondstorage load signal to said second storage gate means.

5. A display system as in claim 3, in which said first and secondstorage devices comprise shift registers.

6. A display system as in claim 4, in which each of said lines comprisesMN characters where M is greater than one and N is greater than zero,said second storage device being operable to store MN sets of bits, saidfirst storage device being operable to store at least M(N+X) sets ofbits where X is greater than zero, said plurality of scans of saidwriting means being an odd integer, whereby a different set of bits aretransferred from said first to said second storage devices at thecompletion ofsaid plurality of scans.

7. A display system as in claim 4, in which one scan of said writingmeans occupies an interval equal to a preselected number of said shiftpulses, said second storage load signal generating means includingcounting means for counting said shift pulses and for terminating saidsecond storage load signal after a count has been reached which is equalto said preselected number.

8. A display system as in claim 3, and input means for producing andapplying sets of bits representing respective new characters to saidfirst storage device, said first storage device comprising first storagegate means for normally connecting said first storage device output withsaid input and for connecting said input means with said first storagedevice input in response to a first storage load signal, and firststorage load signal generating means responsive to the movement of saidsets of bits around said first storage device for generating said firststorage load signal to enter a set of bits from said input means at adesired location relative to the other sets of bits recirculatingthrough said first storage device.

9. A display system as in claim 8, and indicating means responsive tosaid first storage load signal for controlling said count to cause theGAT pulse and cursor to appear at a particular desired located on thescreen.

It is also to be noted that the above functions may be performedmanually rather than utilize the program control PC. For example, if itis desired to move the cursor control backwards (to the left), a signalmay be placed on the FCC] lead by the operation of a switch on thekeyboard KBD such that the counter FBC is incremented one count when thepulse GATD is produced.

DESCRlPTlON OF THE PROGRAM CONTROL (FIG. 8)

As noted above, the system of the present invention is specificallyadapted for the use of microprogramming techniques thereby to provide anextremely flexible display terminal. More specifically, the programcontrol Pc, which utilizes such microprograrnming designs, is shown inFlG. 8 and comprises a counter PBC which may be a conventional 8- bitbinary counter having a count input which receives EOl signals and apreset input which receives PRE1PREB signals to preset the count thereinto produce a reselected coded combination of signals at the output. Theoutput of the counter PBC comprises the parallel coded signals PROl--PROB.

Connected to the counter PBC is a conventional read-only memory PMC,which may be a core memory. In the example under consideration, thememory PMC stores 256 words each one of which is 8-bits long. The memoryPMC includes a decoder which decodes the signals appearing on the leadsPROl-PROB to select one of the 256 words in the memory The selected wordappears on the output leads PMOl-- PMOB as parallel signals. As notedabove, the memory PMC and the counter PBC are conventional inconstruction and are commercially available.

The output leads PMO1PMO8 are connected to the input of a logic elementnetwork LEM which contains conventional logic elements, such as decodersand the like, which are responsive to the coded combinations of signalsappearing on the leads PMOl-PMO8 to perform various functions, such asthe following. it is to be noted that after each function has beenperformed the network LEM produces an 501 pulse to increment the counterPBC to cause the program to go on to the next instruction.

EDIT GROUP l. Move cursor forward one character position.

2. Move cursor backward one character position.

3. Move cursor up one text line.

4. Move cursor down one text linev 5. Move cursor to left-hand characterposition of text line.

6. Move cursor vertically to top of screen.

The above functions are easily performed simply by changing the count inthe cursor counter CBC. For example, if it is desired to move the cursorforward one position each time a new word is entered into the mainmemory, the PC] lead is energized so that the counter CBC is decrcmentedone count when the AND gate A16 is enabled by sensing a word in registerSR2 and producing the appropriate signal on leads PC I and PCZ.

The microprogramming can also perform the following additionalfunctions:

'7. Skip an instruction on finding a preselected flag in a desiredstate. Typical flags to be checked are:

A. Whether the word in input register SR2 represents a character or acommand;

B. Whether the. loading of input register SR2 is completed;

C. Whether the character at the current cursor position is not to beerased. Accordingly, the LEM produces an STP signal, as noted above;

D. Whether the tab is at the current cursor position;

E. Whether the unloading of the output register has been completed;

CIC.

8. Jump to the next address in the program memory. This instructiontransfers the contents of the next address into the program counter andsimultaneously disables the decoder in memory PMC during the operation.

9. Jump to a command from the input register SR2 via the leadsSR2A-SR2H. This instruction jumps to a subroutine at the addressspecified by the contents of the input register SR2. This isaccomplished by storing the next to present memory address on top of thesubroutine stack, incrementing the same and transferring the address tothe program counter PBC via the PREl--PRE8 signal leads.

10. Jump to a subroutine starting at an address contained in thelocation next to the present address. This instruction causes the LEM tostore the address of the next location on the subroutine stack,increment the stack and transfer the address of the next location to thecounter PBC via the PREl-PREB signal lines.

I l. Jump back from a subroutine. This instruction is used at the end ofa subroutine which is entered by means of instructions 9 or ID, above.

The following instructions are used to either add or delete a characterword to the main memory or a tab memory contained in the logic elementnetwork LEM:

l2. Load main memory from the input register SR2, in

which case the STP signal is absent.

13. Load an output register SR3 from the main memories by generating theENA signal, as noted below.

l4. Set tab. This instruction enters a binary l in the tab memory at thecurrent cursor position.

15. Clear tab. This instruction enters a binary 0 in the tab memory atthe current cursor position. In practice, the tab memory may comprise a40-bit circulating memory which is synchronized with the main memory.

Additionally, the microprogram may be adapted to transmit pulses toappropriate logic for setting or clearing flags, initiating routines,and the like to perform one or more of the following functions: enablethe kcyboard KBD', disable the keyboard; clear the input register SR2 orthe output register SR3, and the like.

Additionally, as noted above, commands may come from the input registerSR2 via the lines SR2A-SR2H, which conimands may originate from thekeyboard KBD, from a remote computer via the signal lead RH, and thelike. The command words may be distinguished from the words or sets ofbits representing a character by placing a binary zero in the twohighest order positions of the word. On the other hand, a wordrepresenting a character may have a binary one in one of the two highestorder positions.

While the above commands are illustrative of the type of program whichmay be associated with the system of the present invention, they are notto be interpreted as being a limitation thereof.

DETAILED DESCRlPTlON OF APPARATUS FOR REMOTE TRANSMISSION OF MATERIAL(FIG. 7)

The information contained in the main memory sections of the memoryunits MUAMUH may be transmitted to a remote station utilizing theapparatus illustrated in FIG. 7. Thus, the leads MMAlMMHI of the mainmemory units MUA-MUH are connected to a parallel-input serial-outputshift register SR3 through the respective AND gates A18- A26, which areenabled by the ENA signal from program control PC. The GAT pulse isapplied to the load terminal of shift register SR3 so that the outputsignals appearing on the leads MMAl-MMHI during the occurrence of theSAT signal and the ENA signal will cause the information appearing onthese leads to be entered into the shift register SR3. A signal LCSderived from a local clock CL is applied to the shift terminal of theshift register SR3. The local clock LC may produce shift pulses whichare compatible for use in conjunction with the transmission ofinformation on conventional telephone lines. Thus, the information inthe shift register SR3 writing means to indicate on said medium thelocation at which the next new character will appear.

It]. A display system as in claim 1, in which said decoding meansincludes inhibit means for preventing modulation of said writing meansduring a portion of said plurality of scans to provide a space betweensaid lines ofcharacters.

l]. A display system as in claim I, in which said decoding meansincludes a decoder for decoding the set of bits applied thereto intomodulation signals for the writing means which are available at a numberof decoder outputs, a shift register having inputs greater in numberthan said decoder outputs, means for connecting said decoder outputsindividually to respective ones of a portion of said shift registerinputs, means for connecting said shift register output to said writingmeans whereby the unconnected inputs of said shift register do not causemodulation of the writing means.

12. A system for displaying characters by the cyclic scanning of awriting means comprising, storage means for storing characters dividedinto sets of information bits. said 20 storage means comprising a mainstorage means having output terminals for storing all of the sets ofbits representing all of the characters to be displayed and forproducing said sets of hits at said output terminals at recurrentintervals, and auxiliary storage means connected to said outputterminals of said main storage means for storing the sets of bitsrepresenting the characters to be displayed during a scan of the writingmeans and for sequentially presenting each set of bits at an output, andmodulating means connected to the output of said auxiliary storage meansresponsive to the set of bits appearing at the output for modulating thewriting means to form areas of a character represented by said set ofbits during the scanning of the writing means.

[3. A system for displaying characters as in claim 12, in

which said main and auxiliary storage means comprise recirculatingregisters which operate in synchronism.

14. A system for displaying characters as in claim [2, and a clockcircuit for controlling the operation of said system, said clock circuitincluding shift signal means responsive to said writing means scanningthrough a character to produce a shift signal, said auxiliary storagemeans being responsive to said shift pulse for presenting a new set ofbits representing the next character at said output.

15. A system for displaying characters as in claim 14, in which saidcharacters are formed by a plurality of scans of the writing means, saidclock circuit further comprising line signal means responsive to thelast scan of the writing means in said plurality of scans for generatinga line signal, and gate means responsive to said line signal forconnecting said main and auxiliary storage means together whereby setsof bits are transferred from said main to said auxiliary storage means.

16. A system for displaying characters as in claim 14, and synchronizingmeans connected with and responsive to said clock circuits forsynchronizing the operation of said writing means with said main andauxiliary storage means.

17. A system for displaying characters as in claim l4, and countingmeans for counting said shift signals and for producing an indicatingsignal at a preselected count, input means for producing sets of bitsrepresenting new characters to be displayed, and connecting meansresponsive to said indicating means for connecting together said inputmeans and said main storage means whereby the sets of bits produced bysaid input means are entered into said main storage means.

18. A display system as in claim 17, and indicating means responsive tosaid indicating signal for modulating said writing means to indicate thecharacter position at which the character represented by the sets ofbits produced by said input means will be displayed.

19. A display system as in claim 18, and moving means connected to saidcounting means for varying the count therein to change the indicatedcharacter to a new location.

20. A display system as in claim 18, and control means responsive tosaid indicating signal and the operation of said input means for movingthe indicated character position one character when said set of bitsproduced by said input means is entered into said main storage means.

21. A system for the display of information on a cathode-ray tube havingan electron beam or the like wherein the information comprises a firstplurality of text lines wherein each text line comprises a secondplurality of characters which are formed by a third plurality of scansof the electron beam, said system comprising memory means for storingthe characters to be displayed as respective sets of information bits,said memory means comprising a main memory having an input and an outputfor storing the sets of bits representing all of the characters to bedisplayed, and auxiliary memory connected to said main memory and havingan input and an output for storing all of the sets of bits representingthe second plurality of characters comprising a text line and beingoperable to sequentially present said sets of bits stored in saidauxiliary memory at the output thereof during each of said thirdplurality of scans, scan counting means having a scan count outputcorresponding to each scan in a text line, and character generatingmeans responsive to the particular set of hits at the output of saidauxiliary memory and said scan count output to modulate the electronbeam to form areas of the character represented by the particular set ofbits during the scan represented by the scan count output.

22. A system for the display of information as in claim 2], andcharacter signal means synchronized with the movement of the electronbeam for producing a character signal after a character area has beenformed, said auxiliary memory being responsive to said character signalto present the set of bits representing the next character to bedisplayed at the output thereof.

23. A system for the display of information as in claim 21, in whichsaid scan counting means produces a load auxiliary memory signal at aparticular count, and auxiliary gate means responsive to said loadauxiliary memory signal for connecting said main memory output with saidauxiliary memory input, and shift means operable to transfer sets ofhits from said main memory to said auxiliary memory.

24v A system for the display ofinformation as in claim 21, in which saidmain memory is operable to sequentially produce said sets of bits at theoutput thereof, cursor means including storage counter meanssynchronized with the sequential sets of bits output from said mainmemory for producing a load main memory signal at a particular count,input means for producing a set of bits representing a new character,and main gate means responsive to said load main memory signal forapplying said sets of bits produced by said input means to said mainmemory input.

25. A system for the display of information as in claim 24, and inhibitmeans for disabling said main gate means to prevent the application ofsaid set of bits produced by said input means to said main memory input.

26. A system for the display of information as in claim 24, in whichsaid cursor means is operable to produce a trace on the cathode-ray tubeat the location at which the new character will appear, said storagecounter means including character counting means for producing acharacter signal when a particular character count is reached, said scancounting means producing a load auxiliary memory signal at a particularcount and a cursor signal at a predetermined count, said cursor meansincluding means responsive to said load main memory signal, loadauxiliary memory signal, character signal and said cursor signal formodulating the electron beam to produce said trace.

27. A system for the display ofinformation as in claim 26, in which saidcharacter counting means has a capacity equal to said second pluralityof characters.

28. A system for the display of information as in claim 21, includingtransmission means for transmitting the sets of bits in said memorymeans to a remote location.

29. Position indicating means for a display system of the type having awriting means for forming elemental areas of characters comprising aline of characters during successive scans of the writing means andwherein said line of characters is formed by a plurality of suchsuccessive scans, said position indicating means including charactercounting means for generating a character signal after a preselectedcount is reached corresponding to the horizontal position of thecharacter to be indicated, scan counting means for producing a scansignal after a predetermined count has been reached corresponding to thehorizontal position of the character to be indicated, scan countingmeans for producing a scan signal after a predetermined count has beenreached corresponding to the vertical position at which said indicationis to appear, and modulating means responsive to said character and scansignals for causing said writing means to form a trace at the desiredposition.

30. Position indicating means as in claim 29, in which said writingmeans is adapted to produce a plurality of lines of characters, and linecounting means for counting the lines of said characters and forproducing a line signal corresponding to the line in which the characteris to be indicated, said modulating means being further responsive tosaid line signal for producing said trace in the desire line.

31v Position indicating means as in claim 30, and count varying meansfor varying the count in said character counting means and said linecounting means to change the position of said trace.

1. A display system for displaying at least two lines of characters on amedium which requires a plurality of scans of a writing means to produceeach one of said lines of characters comprising, in combination, storingmeans for storing said characters as respective sets of informationbits, and decoding means for converting the information bits in any oneof said sets into signals for modulating said writing means to producethe character represented by said one set of information bits duringsaid plurality of scans, said storing means comprising a first storagedevice having output terminals for storing the sets of bits representingthe characters to be displayed and for producing said sets of bits atrecurrent intervals at said output terminals, and a second storagedevice connected to said output terminals of said first storage devicefor storing the sets of bits representing the characters to be displayedin one of said lines and for sequentially applying the stored sets ofbits in said second storage device to said decoding means during eachone of said plurality of scans.
 2. A display system as in claim 1, inwhich said second storage device includes input terminals and outputterminals and is operable to recirculate the sets of bits stored thereinand sequentially present each one of said sets of bits at said outputterminals in response to a shift pulse, and shift pulse generating meansfor applying shift pulses to said second storage device.
 3. A displaysystem as in claim 2, in which said first storage device includes inputterminals and is operable to recirculate the sets of bits stored thereinand sequentially present each one of said sets of bits at said outputterminals in response to a shift pulse, and connecting means forconnecting said shift pulse generating means to said first storagedevice to apply said shift pulses to said first storage device.
 4. Adisplay systems in claim 3, in which said second storage device includessecond storage gate means for normally connecting said second storagedevice output terminals with said input terminals and for connectingsaid second storage device input with said first storage device outputterminals in response to a second storage load signal, and secondstorage load signal generating means responsive to the completion ofsaid plurality of scans of the writing means for applying said secondstorage load signal to said second storage gate means.
 5. A displaysystem as in claim 3, in which said first and second storage devicescomprise shift registers.
 6. A display system as in claim 4, in whicheach of said lines comprises MN characters where M is greater than oneand N is greater than zero, said second storage device being operable tostore MN sets of bits, said first storage device being operable to storeat least M(N+X) sets of bits where X is greater than zero, saidplurality of scans of said writing means being an odd integer, whereby adifferent set of bits are transferred from said first to said secondstorage devices at the completion of said plurality of scans.
 7. Adisplay system as in claim 4, in which one scan of said writing meansoccupies an interval equal to a preselected number of said shift pulses,said second storage load signal generating means including countingmeans for counting said shift pulses and for terminating said secondstorage load signal after a count has been reached which is equal tosaid preselected number.
 8. A display system as in claim 3, and inputmeans for producing and applying sets of bits representing respectivenew characters to said first storage device, said first storage devicecomprising first storage gate means for normally connecting said firststorage device output with said input and for connecting said inputmeans with said first storage device input in response to a firststorage load signal, and first storage load signal generating meansresponsive to the movement of said sets of bits around said firststorage device for generating said first storage load signal to enter aset of bits from said input means at a desired location relative to theother sets of bits recirculating through said first storage device.
 9. Adisplay system as in claim 8, and indicating means responsive to saidfirst storage load signal for controlling said writing means to indicateon said medium the location at which the next new character will appear.10. A display system as in claim 1, in which said decoding meansincludes inhibit means for preventing modulation of said writing meansduring a portion of said plurality of scans to provide a space betweensaid lines of characters.
 11. A display system as in claim 1, in whichsaid decoding means includes a decoder for decoding the set of bitsapplied thereto into modulation signals for the writing means which areavailable at a number of decoder outputs, a shift register having inputsgreater in number than said decoder outputs, means for connecting saiddecoder outputs individually to respective ones of a portion of saidshift register inputs, means for connecting said shift register outputto said writing means whereby the unconnected inputs of said shiftregister do not cause modulation of the writing means.
 12. A system fordisplaying characters by the cyclic scanning of a writing meanscomprising, storage means for storing characters divided into sets ofinformation bits, said storage means comprising a main storage meanshaving output terminals for storing all of the sets of bits representingall of the characters to be displayed and for producing said sets ofbits at said output terminals at recurrent intervals, and auxiliarystorage means connected to said output terminals of said main storagemeans for storing the sets of bits representing the characters to bedisplayed during a scan of the writing means and for sequentiallypresenting each set of bits at an output, and modulating means connectedto the output of said auxiliary storage means responsive to the set ofbits appearing at the output for modulating the writing means to formareas of a character represented by said set of bits during the scanningof the writing means.
 13. A system for displaying characters as in claim12, in which said main and auxiliary storage means compriserecirculating registers which operate in synchronism.
 14. A system fordisplaying characters as in claim 12, and a clock circuit forcontrolling the operation of said system, said clock circuit includingshift signal means responsive to said writing means scanning through acharacter to produce a shift signal, said auxiliary storage means beingresponsive to said shift pulse for presenting a new set of bitsrepresenting the next character at said output.
 15. A system fordisplaying characters as in claim 14, in which said characters areformed by a plurality of scans of the writing means, said clock circuitfurther comprising line signal means responsive to the last scan of thewriting means in said plurality of scans for generating a line signal,and gate means responsive to said line signal for connecting said mainand auxiliary storage means together whereby sets of bits aretransferred from said main to said auxiliary storage means.
 16. A systemfor displaying characters as in claim 14, and synchronizing meansconnected with and responsive to said clock circuits for synchronizingthe operation of said writing means with said main and auxiliary storagemeans.
 17. A system for displaying characters as in claim 14, andcounting means for counting said shift signals and for producing anindicating signal at a preselected count, input means for producing setsof bits representing new characters to be displayed, and connectingmeans rEsponsive to said indicating means for connecting together saidinput means and said main storage means whereby the sets of bitsproduced by said input means are entered into said main storage means.18. A display system as in claim 17, and indicating means responsive tosaid indicating signal for modulating said writing means to indicate thecharacter position at which the character represented by the sets ofbits produced by said input means will be displayed.
 19. A displaysystem as in claim 18, and moving means connected to said counting meansfor varying the count therein to change the indicated character to a newlocation.
 20. A display system as in claim 18, and control meansresponsive to said indicating signal and the operation of said inputmeans for moving the indicated character position one character whensaid set of bits produced by said input means is entered into said mainstorage means.
 21. A system for the display of information on acathode-ray tube having an electron beam or the like wherein theinformation comprises a first plurality of text lines wherein each textline comprises a second plurality of characters which are formed by athird plurality of scans of the electron beam, said system comprisingmemory means for storing the characters to be displayed as respectivesets of information bits, said memory means comprising a main memoryhaving an input and an output for storing the sets of bits representingall of the characters to be displayed, and auxiliary memory connected tosaid main memory and having an input and an output for storing all ofthe sets of bits representing the second plurality of characterscomprising a text line and being operable to sequentially present saidsets of bits stored in said auxiliary memory at the output thereofduring each of said third plurality of scans, scan counting means havinga scan count output corresponding to each scan in a text line, andcharacter generating means responsive to the particular set of bits atthe output of said auxiliary memory and said scan count output tomodulate the electron beam to form areas of the character represented bythe particular set of bits during the scan represented by the scan countoutput.
 22. A system for the display of information as in claim 21, andcharacter signal means synchronized with the movement of the electronbeam for producing a character signal after a character area has beenformed, said auxiliary memory being responsive to said character signalto present the set of bits representing the next character to bedisplayed at the output thereof.
 23. A system for the display ofinformation as in claim 21, in which said scan counting means produces aload auxiliary memory signal at a particular count, and auxiliary gatemeans responsive to said load auxiliary memory signal for connectingsaid main memory output with said auxiliary memory input, and shiftmeans operable to transfer sets of bits from said main memory to saidauxiliary memory.
 24. A system for the display of information as inclaim 21, in which said main memory is operable to sequentially producesaid sets of bits at the output thereof, cursor means including storagecounter means synchronized with the sequential sets of bits output fromsaid main memory for producing a load main memory signal at a particularcount, input means for producing a set of bits representing a newcharacter, and main gate means responsive to said load main memorysignal for applying said sets of bits produced by said input means tosaid main memory input.
 25. A system for the display of information asin claim 24, and inhibit means for disabling said main gate means toprevent the application of said set of bits produced by said input meansto said main memory input.
 26. A system for the display of informationas in claim 24, in which said cursor means is operable to produce atrace on the cathode-ray tube at the location at which the new characterwill appear, said storage counter means including character countingmeans for producing a character signal when a particular character countis reached, said scan counting means producing a load auxiliary memorysignal at a particular count and a cursor signal at a predeterminedcount, said cursor means including means responsive to said load mainmemory signal, load auxiliary memory signal, character signal and saidcursor signal for modulating the electron beam to produce said trace.27. A system for the display of information as in claim 26, in whichsaid character counting means has a capacity equal to said secondplurality of characters.
 28. A system for the display of information asin claim 21, including transmission means for transmitting the sets ofbits in said memory means to a remote location.
 29. Position indicatingmeans for a display system of the type having a writing means forforming elemental areas of characters comprising a line of charactersduring successive scans of the writing means and wherein said line ofcharacters is formed by a plurality of such successive scans, saidposition indicating means including character counting means forgenerating a character signal after a preselected count is reachedcorresponding to the horizontal position of the character to beindicated, scan counting means for producing a scan signal after apredetermined count has been reached corresponding to the horizontalposition of the character to be indicated, scan counting means forproducing a scan signal after a predetermined count has been reachedcorresponding to the vertical position at which said indication is toappear, and modulating means responsive to said character and scansignals for causing said writing means to form a trace at the desiredposition.
 30. Position indicating means as in claim 29, in which saidwriting means is adapted to produce a plurality of lines of characters,and line counting means for counting the lines of said characters andfor producing a line signal corresponding to the line in which thecharacter is to be indicated, said modulating means being furtherresponsive to said line signal for producing said trace in the desireline.
 31. Position indicating means as in claim 30, and count varyingmeans for varying the count in said character counting means and saidline counting means to change the position of said trace.